Dual-Port PCM Architecture for Network Processing
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چکیده
This paper describes a virtually pipelined memory architecture built on a dual-port phase change memory (PCM) substrate for high performance networking applications. The proposed dual-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes, ensuring that the proposed memory architecture can provide the large bandwidth and bank parallelism necessary for such applications. We analyze the performance of the proposed architecture using queueing theory and statistical information obtained by processing network packet traces using PacketBench, and show that the proposed innovations can reduce the expected read delay by 20–30× over conventional single-port PCM for 0.45–2.2× overhead.
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